A processor device may have a generic asynchronous external memory interface (EMIF) that associates different access timing characteristics with different memory spaces or ‘chip selects’. It is also common in processor devices to have a DMA (dedicated memory access) controller which has access to those memory spaces or ‘chip selects’. A common type of flash memory in the industry is the “page mode” flash memory which requires a certain set of access timing characteristics for the first access of a “page” or block of flash memory locations, but then allows a different (much faster) set of access timing characteristics for access to the remaining data in the page. If a processor device does not have an EMIF that specifically implements direct support of page mode for flash memory, then some performance may be lost when accessing such a flash memory because the slower access timing characteristics of the first access is used for all accesses to the page.